PDF] Chip scale package implementation challenges

The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. In the process of building the Consortium CSP test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of test vehicles. We also discuss the most current package isothermal aging to 2000 hours at 100/spl deg/C and 125/spl deg/C and thermal cycling test results to 1700 cycles in the range of -30 to 100/spl deg/C.

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PDF] Chip scale package implementation challenges

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PDF] Chip scale package implementation challenges

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